This invention relates to a sense circuit suitable for various buffer circuits in a semiconductor memory.
At present, a large-scale dynamic random-access memory (dRAM) is formed of MOS (metal oxide semiconductor) transistors. External logic circuits, which apply input signals and control signals to such a semiconductor memory, are usually formed of bipolar transistors. The semiconductor memory is operated at MOS logic signal levels, while the external logic circuits are operated at TTL (transistor-to-transistor logic) signal levels. In the MOS logic-level system used in the MOS semiconductor memory, a "HIGH" level of signals is set to a high level Vcc of a power source voltage, for example, +5 volts, while a "LOW" level is set to a low level Vss (ground) of the power source voltage. In the TTL level system used in the external logic circuits, a "HIGH" level of logic signals ranges from +2.4 to +6.5 volts, and a "LOW" level ranges from -1 to +0.8 volt. Since the external logic circuits and the semiconductor memory are different in the logic levels of signals, as described above, buffer circuits are required in the semiconductor memory, in order to convert the TTL signal levels into the MOS logic signal levels. Such buffer circuits may be classified into an address buffer circuit for an address input signal, a data input buffer circuit for a data input signal, and a control signal buffer circuit for a control signal. Among them, the address buffer circuit is typical.
A well known buffer circuit comprises a sense amplifier having first and second inputs (nodes), and first and second transfer gates. An externally applied input signal is coupled to the first input of the sense amplifier via the first transfer gate. A common reference voltage source is coupled to the second input of the sense amplifier via the second transfer gate. The externally applied input signal makes excursions between high and low levels. The reference voltage is set to a predetermined voltage level which is almost midway between the high and low levels of the input signal.
The first and second transfer gates are clocked by a common clock signal (control signal). As a result, the input signal and the reference voltage are latched in the first and the second inputs of the sense amplifier, respectively. By comparing the input signal voltage level with the reference voltage level, the sense amplifier senses the input signal, and amplifies it. Usually the sense amplifier provides complementary outputs. With the prior art buffer circuit, since the reference voltage is set to a fixed level, if a variation in the voltage level of an input signal occurs, a difference in level between the input signal voltage and the reference voltage would be decreased, which might possibly reduce an operational margin of the buffer circuit.
To solve the above problem, improved buffer circuits have been proposed.
With a circuit disclosed in Japanese Patent Disclosure (kokai) No. 56-134385, a reference voltage source is designed to generate a reference voltage whose level is midway between the "HIGH" and "LOW" levels in the TTL logic system, and vary the reference voltage level in opposite phase relation to a variation in the voltage level of the input signal.
The level-shift operation is performed outside a transfer gate, so that the level-shifted reference voltage is coupled to a node of a sense amplifier via the transfer gate. However, since the reference voltage varies with a change in the input signal, a finite delay will occur in the variation of the reference voltage. Accordingly, when the input signal is latched, if the reference voltage variation is not completed, the operational margin of the circuit becomes small.
An improved address buffer circuit is disclosed in Japanese laid open Patent Publication No. 56-134385.
In this address buffer circuit, a reference voltage source, which responds to an externally applied input signal, as in the above-mentioned buffer circuit, is designed to be operated by a control signal before the first and the second transfer gates are clocked. However, in order to operate the reference voltage source before the address signal is latched in the first input of the sense amplifier, it is required that a clocking timing of the first and the second transfer gates be delayed. This will reduce the margin for a row address hold time tRAH where the buffer circuit is used for a row address buffer circuit of a semiconductor memory.